1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a conductive layer having a three-dimensional shape, such as a storage node of a capacitor, using a dielectric layer as a mold.
2. Description of the Related Art
The elements of a semiconductor device are becoming more densely integrated to improve the processing speed and increase the memory capacity of the resulting devices. Manufacturing processes for 16M and 64M dynamic random access memory (DRAM) devices are being replaced by 256M manufacturing processes, and mass production techniques for 1G devices are rapidly evolving. As the design rules for semiconductor devices decrease, the area occupied by memory elements (e.g., a capacitor) need to be decreased. However, it becomes difficult to provide such a capacitor to meet the design requirement, and yet still obtain sufficient capacitance to properly operate within the DRAM device.
To overcome the difficulties in forming such a capacitor, methods for increasing the effective surface area of a dielectric layer have been introduced, for example, forming three-dimensional capacitor structures, such as a stack type capacitor, a trench type capacitor, or a cylinder type capacitor.
In particular, a method for forming a three-dimensional storage node using a mold has been suggested. In order to increase the surface area of a three-dimensional capacitor occupying only a limited space due to a decreased and restricted cell area, the height of the three-dimensional storage node must be increased. However, increasing the height of a capacitor causes difficulties in performing an etching process for forming a three-dimensional capacitor, in particular, an etching process for patterning a mold.
FIG. 1 is a vertical scanning electron microscope (SEM) image of a mold patterned for forming a three-dimensional storage node. FIG. 2 is a vertical SEM image of a capacitor including a three-dimensional storage node formed using the mold shown in FIG. 1. FIG. 3 is a vertical SEM image of the bottom portions of a three-dimensional storage node which illustrates certain problems with a capacitor including the three-dimensional storage node. FIG. 4 is a graph showing the deterioration of leakage current characteristics of a capacitor including a three-dimensional storage node.
Referring to FIG. 1, a conventional method for forming a semiconductor device including a storage node of a capacitor includes a step of forming a layer of silicon oxide on a semiconductor substrate, with the silicon oxide layer being used later as a mold layer. Then mold layer is then etched to form a through hole exposing a lower contact, such as a buried contact (BC) or other structure. The mold layer may generally be thick, usually with a thickness of between several thousands of angstroms to 10000 xc3x85. The reason the mold layer is so thick is that the height of a storage node or capacitor to be formed later is dependent on the thickness of this mold layer.
However, since the mold layer is relatively thick, it is difficult to obtain a good sidewall profile of the through hole, which is formed by selectively etching the mold layer. As shown in FIG. 1, it is hard to obtain a sufficient critical dimension (CD) at the bottom portion of the through hole exposing the buried contact. Note that the top CD of the through hole is greater than the bottom CD of the through hole, and thus the through hole has an inclined sidewall. With the typical processes for etching a thick mold layer, it is hard to obtain a sufficient bottom CD of the through hole because it is difficult to obtain a through hole having a sidewall that is perpendicular to the bottom of the through hole.
Referring to FIG. 2, after forming the mold having the through hole, in subsequent process steps a storage node layer is deposited on the mold and along the sidewalls and bottom of the through hole. Since the deposited storage node layer conforms to the shape of the mold, a storage node can be formed into a three-dimensional structure (e.g., a cylinder type or stack type structure) by patterning or separating the storage node layer to achieve the requisite shaped through hole. The mold is removed using the storage node as a mask, and then a dielectric layer and a plate node are formed on the storage node, thereby forming a capacitor.
It is evident that the shape of the capacitor described above depends on the shape of the storage node. More specifically, the shape of the storage node substantially depends on the shape or profile of the through hole (or the mold). As described above, if the bottom CD of the through hole of the mold is smaller than the top CD of the through hole, i.e., if the sidewall of the through hole (or the mold) is inclined, the resulting storage node that is formed is also inclined, and thus the bottom CD of the capacitor is inevitably narrower than the top CD of the capacitor, as is illustrated in FIG. 2.
When the bottom CD of the capacitor is narrower than the top CD of the capacitor, the capacitor or storage node is structurally unstable, and thus the storage node or capacitor may tilt to one side or collapse. In addition, when the bottom CD of the capacitor is narrower than the top CD of the capacitor, the aspect ratio of a gap between adjacent storage nodes is deteriorated. Accordingly, the step coverage of the dielectric layer or the plate node may deteriorate at the bottom of the gap between adjacent storage nodes, and thus the electrical characteristics of the whole capacitor may deteriorate.
FIG. 3 shows a deteriorated aspect ratio of the gap 60 between storage nodes whose bottom CDs are narrower than the top CDs. In other words, the opening of the gap between the storage nodes is narrower than the bottom portion of the gap between the storage nodes. As a result, the step coverage of the dielectric layer or plate node may be deteriorated.
FIG. 4 shows that if the step coverage of the dielectric layer or plate node is deteriorated, the electrical characteristics of a capacitor, such as leakage current characteristics, are deteriorated (essentially an increase in leakage current is experienced).
Also, if the sidewalls of a three-dimensional storage node are inclined, i.e., if the bottom CD of the storage node is narrower than the top CD of the storage node, the misalignment margins between the storage node and a lower buried contact become narrower. Accordingly, resistance may increase due to the decrease of the contact area between the lower part of the storage node and the buried contact.
To solve the above-described problems, it is an object of the present invention to provide a method for manufacturing a semiconductor device, which is capable of preventing the sidewalls of three-dimensional storage nodes from being inclined due to the inclined sidewalls of a dielectric layer used as a mold for forming such storage nodes.
Accordingly, to achieve the above object, there is provided a method for manufacturing a semiconductor device according to an aspect of the present invention. The method includes forming a dielectric layer on a substrate, with the dielectric layer having an intrinsic etch rate which increases with the depth (or thickness) of the dielectric layer. This variable intrinsic etch rate is achieved by changing one of a plurality of deposition variables. The dielectric layer is selectively etched in order to form a through hole that passes through the dielectric layer. A conductive layer, i.e., a storage node of a capacitor, is then formed in the through hole.
In selectively etching the dielectric layer, as the depth to which the dielectric layer is etched increases, the etch rate of the dielectric layer increases. The etch rate of the lowest or bottom portion of the dielectric layer may be 1.1-10 times greater than the etch rate of the highest or top portion of the dielectric layer.
The dielectric layer may be formed of silicon oxide deposited by a chemical vapor deposition (CVD)-based method. With regard to the deposition parameters that may be varied, during the CVD method, the plasma power of the chemical vapor deposition may be gradually increased, and the deposition temperature of the chemical vapor deposition may be gradually increased. The content of a silicon source of the chemical vapor deposition, which is used to form silicon oxide, may be gradually decreased relative to an oxidation source, which oxidation source is also used to form silicon oxide in combination with the silicon source. The pressure within the deposition chamber used in the chemical vapor deposition process may be gradually decreased. Also, the gap between a shower head for supplying a source required for a deposition reaction and the semiconductor substrate of the chemical vapor deposition may be gradually decreased.
The chemical vapor deposition may be thermal chemical vapor deposition or plasma-enhanced chemical vapor deposition.
The dielectric layer (or mold layer) may be formed of a borophosphosilicate glass (BPSG) layer or a phosphosilicate glass (PSG) layer having a doping concentration which gradually varies along the direction of the depth or thickness of the dielectric layer. For example, the dielectric layer may be formed so that the doping concentration increases gradually from the top portion of the dielectric layer to the bottom of the dielectric layer.
The bottom critical dimension (CD) of the through hole may be substantially equal to the top CD of the dielectric layer. Alternatively, the bottom CD of the through hole may be substantially greater than the top CD of the through hole. In either case, the resulting storage node is structurally stable.
The dielectric layer may be selectively etched by a wet etching-based etching method or a dry (anisotropic) etching-based etching method.
According to the embodiment of the present invention, it is possible to prevent the sidewalls of three-dimensional storage nodes from being inclined due to the inclined sidewalls of a mold introduced for forming such storage nodes.